1. Field of the Invention
The present invention relates to flash EPROM cells and methods for their construction. More particularly, the current invention relates to reducing leakage during source erase of a flash EPROM cell. More specifically, the present invention provides a new erase technique that reduces leakage during source erase of a flash EPROM cell.
2. Discussion of Related Art
Erasable programmable read-only memory (EPROM) is a form of non-volatile memory. Non-volatile memory devices retain information when power to the device is interrupted and are important in the design of wireless and portable electronic devices. Non-volatile storage choices range from mask read-only memory (ROM), ultraviolet EPROM (UV-EPROM), flash EPROM and electrically erasable EPROM (EEPROM).
EPROM devices typically lack the density of ROM disks but are more flexible since coded changes can be readily accommodated. EPROM devices offer the further advantage of rapid access since reading and writing to these types of devices is not delayed by latency periods.
Flash EPROM offers some of the advantages of EEPROM with the lower cost of UV-EPROM. All forms of EPROM use electrical injection methods to program individual memory cells but differ in the method of memory cell erasure. Ultraviolet light irradiation is used to erase UV-EPROM memory cells. This method is non-selective and requires removal of memory cells from the system for erasure. EEPROM systems use Fowler-Nordheim tunneling to erase single cells which offers reprogramming flexibility, high density and convenience, since removal of memory cells from the device is not required for erasure.
Flash EPROM also uses Fowler-Nordheim tunneling for non-selective memory cell erasure. Thus, flash EPROM provides the convenience and high density of EEPROM with the low cost of conventional UV-EPROM. Therefore, flash EPROM has become the storage method of choice in many portable consumer devices such as cell phones and hand held personal computers.
Two different methods, which employ Fowler-Nordheim tunneling, are typically used to erase flash EPROM cells. In channel or substrate erase, a positive bias of about 10.0 V is applied to the substrate of the memory cell. Similarly, a negative bias of about -5.0 V is applied to the gate of the memory cell. Electron tunneling from the gate to the substrate then erases the memory cell. Channel erase requires source isolation by the triple well process, which is complicated and expensive.
Source erase is identical to substrate erase except that a positive bias of about 5.0 V is applied to the source of the memory cell while a negative bias of about -10.0 V is applied to the gate of the memory cell. Since source erase does not require source isolation by the triple well process it is simpler and less expensive to implement than channel erase.
However, a significant problem with source erase of flash EPROM cells is source diode leakage to the substrate during erasure. Source diode leakage lengthens the time required to erase a flash EPROM, degrades performance and must be minimized to increase source erase speed.
Three different mechanisms have been identified as contributing to source diode leakage during source erase. Thermal leakage, which is intrinsic to any tunneling process, is small and independent of electric field. Avalanche multiplication is electric field dependent and can become very large if the cell is not optimized during fabrication.
Band to band tunneling leakage is a fundamental problem with source erase, particularly at high electrical field and reduced channel width (C. Chang et al., Tech. Dig. IEDM, 714, 1987; H. Kume et al., Tech. Dig. IEDM, 560, 1987). Band to band tunneling leakage wastes power since some of the diode current is dissipated in the substrate during erasure. Furthermore, constant source voltage is difficult to maintain in the presence of this type of leakage, which places significant demand on the charge pump capacitor. Thus, the difficulties caused by band to band leakage in generating and maintaining the voltage required to erase the device are frequently the limiting factor in erasure of flash EPROM cells.
FIG. 1 illustrates a conventional method used to erase a flash EPROM cell. Shown in FIG. 1 are conventional source and gate pulse profiles as a function of time. The source pulse height 102 is about 5.0 V while the gate pulse height 104 is about -10.0 V during memory cell erasure. The gate pulse height 102 and source pulse height 104 strongly affect the erase speed and are typically adjusted to maximize electron tunneling from the floating gate to the source. However, optimizing erasure rate increases the magnitude of the source to gate electric field, thus causing significant band to band tunneling leakage.
The relationship of conventional erase techniques and band to band tunneling leakage may be understood with reference to FIGS. 2, 3 and 4. Shown in FIG. 2 is a stacked gate 220 disposed on a semiconductor substrate 212. The stacked gate 220 may be made by conventional methods well known in the art. Stacked gate 220 is comprised of tunnel oxide layer 204, a floating gate 206, insulating layer 208 and the control gate 210. Floating gate 206 and control gate 210 are typically different polysilicon layers. Source 216 forms an electrical junction with the stacked gate 220 at the source edge 222 under the stacked gate edge 224.
Typically, in a programmed cell a residual electric field of about -2.0 V to about -3.0 V exists between the source 216 and the stacked gate 220. Thus, applying a voltage of between about -10.0 V and about -12.0 V to the control gate 210 instantaneously results in an effective voltage of between about -12.0 V to about -15.0 V in floating gate 206. Therefore, a high electric field exists in the floating gate 206 upon initial voltage application until some of the electrons tunnel to source 216. The voltage in the floating gate eventually reaches a constant value as excess electrons tunnel to the source.
The dependence of floating gate voltage on time after initial voltage application to the control gate is graphically depicted in FIG. 3. The vertical axis represents the voltage of the floating gate while the horizontal axis represents time. Line 302 in FIG. 3 reaches a constant value as a function of time. The electric field in the floating gate changes from an initial value of about -12.0 V to a constant value of about -6.0 V within about 100 .mu.sec. Thus, the electric field in the floating is diminished by a factor of about 2 during about 100 .mu.sec. The change in voltage reflects tunneling of electrons to the source.
However, as previously mentioned, the high initial electric field in the floating gate results in a large source diode current due to band to band tunneling leakage. FIG. 4 graphically illustrates the relationship between source diode leakage caused by band to band tunneling as a function of time after initial application of voltage to the control gate. The horizontal axis represents the amount of leakage to the substrate from the source diode caused by band to band tunneling while the horizontal axis represents time. Line 402 rapidly decays from an initial value of about 100 .mu.A to a constant value of about 10 nA in about 100 .mu.sec. Thus, the amount of current leaked into the source is diminished by a factor of about ten in 100 .mu.sec. As can be seen from FIG. 4 a significant percentage of source diode leakage occurs after initial application of voltage to the control gate.
FIGS. 3 and 4 demonstrate that a significant problem in source erase is the high initial electric field in the floating gate, which consequently results in high initial source diode leakage. As electrons are removed from the floating gate source diode leakage is also reduced.
It has become apparent that as flash EPROM devices shrink in size and increase in density that new methods of reducing source diode leakage are necessary. Thus, what is needed is a new erase technique that minimizes band to band tunneling leakage during source erase. More particularly, what is required is a method that reduces the magnitude of source diode leakage caused by high initial electric field in the floating gate